1. Field of the Invention
The present invention relates to an integrated circuit using a standard cell design methodology in which gate array basic cells are mixedly-mounted on a circuit which is constructed by use of the standard cells.
2. Description of the Prior Art
A fulcustom IC is suitable for the case where high performance ICs are mass-produced, but it has such a disadvantage that a period of time required from design process to manufacture process is long. On the contrary, a semicustom IC is suitable for the case where a user-oriented LSI should be developed in a short period of time if patterns of the logic cells, etc. are executed according to design automation (DA) by using a computer. Sometimes design automation by using the computer can be introduced into the fulcustom design. In this case, mainly such automation is applied to prediction of circuit operation and pattern verification. Standardization of design automation has not been carried out in other design aspects and therefore the designer has proceeded circuit design in an interactive manner with manual intervention, i.e., so-called computer-aided design approach has been introduced.
Meanwhile, the semicustom approach is design automation by use of the computer because design techniques are standardized, and the gate array design methodology and the standard cell design methodology have been known. According to the gate array design methodology, a master chip on which basic cells are arranged in a matrix form is prepared in advance, then only metal wiring layer design on the basic cells is executed, and then the user oriented LSI can be developed in a short period of time by laying wiring connection of the melt wiring layers. Factors to enable development of the gate array in a short period of time are (a) the manufacturing step is only a wiring step for the metal wiring layer; (b) packaging and evaluation term is short since chip size, number of pads, etc. are determined previously; and (c) verification of function can be conducted quickly and troubles due to miss can be reduced smaller since verified cells are used and LSIs are designed and logically verified by means of design automation.
While, the standard cell design methodology is resemble to the gate array design methodology in a respect that the integrated circuit to satisfy desired logical functions can be achieved by use of a cell library in which information of the cells being designed and verified manually or by the computer in advance are stored. However, usually the cells used in the standard cell architecture have logical functions like a simple logic gate and a flip-flop, and in many cases have rectangular patterns with a uniform height H and widths W, the width W is set to be variable geometrically. As shown in FIG. 1, normally the standard cells (SC1, SC2, SC3, SC4, SC5, . . . ) 100 are never spread all over the surface of the chip 101. In other words, wiring channel regions in which the metal wirings to connect the standard cells 100 are formed between device rows on the chip 101. The empty space 102 in which no standard cell 100 is arranged still remain in each device row as regions in which no functional device such as transistor is formed and which is used only to form the metal wirings.
In the integrated circuit being constructed by use of such standard cells, when design change is needed due to circuit change, etc., only the metal wirings may be modified unless the number of transistors and the configuration are still not changed, but further transistors must be added newly if extra transistors are needed. In this case, design change cannot be satisfied only by changing the metal wirings and thus preceding steps rather than the last few wiring steps in the fabrication process, i.e., selective ion-implantation steps to form diffusion layers of the source/drain regions constituting the transistors, CVD step and RIE step to form the polysilicon layer, must be changed. Of course, change of the mask patterns used in these steps is also added to such change of steps. Therefore, if the circuit change with additional arrangement of the transistors is demanded, turn around time of the LSI using the standard cell approach is extended.
On the contrary, the gate array design style is a design in which a desired circuit is constructed by providing the wirings to the basic cells which are arranged regularly and fixedly on the matrix. The basic cells used in the gate array approach are identical cells which have no logic function by themselves, simple logic cells such as simple gates, flip-flop, etc. which are formed by connecting one or plural basic cells simply, and the like. In the integrated circuit using such gate array design style, especially the circuit called “as whole surface spread-over type”, the uniform transistor array are arranged all over the chip surface in advance and then various circuits can be constructed with the use of a part of the array. In the gate array architecture, like the standard cell architecture, the transistors not used also remain as they are. Therefore, if the circuit change is demanded, such circuit change can be treated only by changing the metal wirings while using such unused transistors. In addition, since a master-slice prepared previously is used in the gate array chip, a term for last few manufacturing steps of metal wirings is required, so that the circuit can be developed in a short period of time. However, since only the basic cells being prepared beforehand can be used upon design of the circuit in the gate array design, there has been such a disadvantage that a margin in circuit design is limited, for example, the size of the transistors cannot be reduced
Memory, CPU core, ALU, A/D converter, D/A converter, display, and various I/O circuits are included almost surely in the large scale circuit system. And as the circuit scale is made huge, the necessity to mount such subsystems on the same chip arisen. Hence, recently memory/logic mixedly mounting design methodology, analogue/digital mixedly mounting design methodology, etc. become important. For this reason, there have been developed a composite gate array in which memory leased regions are provided in a part of the master chip, or “an embedded array” in which manufacturing of the substrate and design of the gate array portion can be advanced simultaneously by combining a logic circuit area consisting of the channelless gate array and the large capacity memory or the processor core on the same chip. This array is highly observed recently since the integration density and flexibility like the standard cell can be obtained and the development term can be shortened like the gate array. In FIG. 2, a case is shown wherein the channelless type gate array region 221 and the channelless type standard cell region 222 together with a megacell 213 and megafunctions 211, 212 are formed on the chip 201. The “megacell 213” means the cell which has fixed layout pattern of the cell, and the representative megacell is memory such as ROM or RAM, multiplier, etc. whose performance depends on the layout. The “megafunctions 211, 212” means the circuit which can be implemented by combination of macrocells on the layout though it is treated theoretically as a lump of cells, and the representative megafunction is ALU, CPU core, etc. whose chip integration degree is affected by connection relationship between the megafunction and other blocks. The channelless type gate array region 221 is a gate array region in which the wiring channel region is eliminated, the gate array is spread over the whole logic circuit area 221, and the basic cell can be used as either the wirings or functional block according to the demand. The channelless type standard cell region 222 is a region in which the wiring channel region is eliminated and the standard cells is spread over the whole logic circuit area 222.
As stated above, in the integrated circuit using the standard cell architecture in the prior art, if the circuit change with additional arrangement of the transistors is demanded, “pre-stage-steps” of all steps to manufacture the integrated circuit, which need a long period of time necessary for process such as formation of the source/drain diffusion layers or the gate polysilicon layer, must be changed. As a result, for example, though the metal wiring step takes about two days, normally “pre-stage-steps” including the diffusion step applied below the metal wiring layer take more than seven days.
In contrast, in the integrated circuit using the gate array architecture in the prior art, since design change can be effected only by changing the wirings, there has been such an advantage that the circuit change can be easily carried out. Conversely, since the basic cells used are simple, a margin in circuit design is low rather than the standard cell layout. For this reason, in the integrated circuit using the gate array layout, there have been disadvantages that circuit design becomes difficult and sometimes it becomes difficult to achieve desired circuit performance. For instance, such a disadvantage is caused that, if it is desired to reduce power consumption in the particular circuit, excessive current are passed because the sizes of the transistors are fixed.
These problems are caused similarly in the embedded array shown in FIG. 2. Even the region 222 in which the standard cells are spread all over the logic circuit area and the region 221 in which the gate array is spread all over the logic circuit area cannot be escaped from natural performances end characteristics of the standard cells and the gate array, and therefore they cannot overcome the natural problems included in the conventional cells at all.